For system-on-chip applications, embedded memories on the chip are typically implemented by either using hard macros (for large bit requirements) or by using memory compilers to generate a wide range of memories with various word width and depth options. A typical system-on-chip product may contain tens to a few hundreds of memory instances of various sizes, memory types and performance requirements. Each such memory instance comes with its complete set of peripheral circuitry, array termination structures, and may even contain redundant elements to enable repair of defective bits. Some memory arrays can be quite small, therefore the overhead from terminating array structures is higher than in larger memory arrays.
FIG. 1 is a block diagram illustrating a conventional system-on-chip product. The system-on-chip 10 is shown having multiple memory arrays 12 that vary in memory type and size. FIG. 2 is a block diagram illustrating a conventional memory array 12 showing that each memory array 12 includes its own periphery circuitry. The periphery circuitry may include a row decoder 14 along one edge, a sense amplifier 16 along a second edge, and terminating structures 18 along the two remaining edges. The periphery circuitry may also include multiplexing and I/O's not shown.
The terminating structures 18 function to terminate the memory array 12, and typically mimic to some extent the structure of the bit cells comprising the memory array 12 and only qualitatively reproduce cells inside the array. Although any edge bit is surrounded by a similar layout topology as any bit further inside the array 12, terminating structures typically assume simpler forms and are only intended for a smooth transition between highly dense memory areas to low density logic areas. Terminating structures 18 also may contain additional power ring and well connection structures, but do not typically have a mirror line.
FIG. 3 is a block diagram showing a conventional center row decoder memory architecture where two memory arrays 12 share a center row decoder 14. Although in this architecture, only one row decoder is needed for two arrays 12, each memory array 12 still requires a set of terminating edge structures 18, and only two arrays 12 can be combined along the edge occupied by the row decoder. Although the periphery circuitry is not included in the terminating structures, including the periphery circuitry in each of the tens or hundreds of the memory arrays 12 adds significantly to chip overhead. Accordingly, what is needed is a method and system for reconfiguring memory arrays 12 in order to reduce the peripheral overhead and improve memory array effective density. The present invention addresses such a need.